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[FreeTutorials.Us] Udemy - Learn VHDL and FPGA Development

文件类型 收录时间 最后活跃 资源热度 文件大小 文件数量
视频 2021-4-28 19:21 2024-12-16 16:01 217 1.93 GB 59
磁力链接
magnet:?xt=urn:btih:de3d7c39abbbce16fea5e882b0152398cff8c485
迅雷链接
thunder://QUFtYWduZXQ6P3h0PXVybjpidGloOmRlM2Q3YzM5YWJiYmNlMTZmZWE1ZTg4MmIwMTUyMzk4Y2ZmOGM0ODVaWg==
二维码链接
[FreeTutorials.Us] Udemy - Learn VHDL and FPGA Development的二维码
种子下载(838888不存储任何种子文件)
种子下载线路1(迅雷)--推荐
种子下载线路2(比特彗星)
种子下载线路3(torcache)
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相关链接

FreeTutorials Us Udemy - Learn VHDL and FPGA Development

文件列表
  1. 10. Xilinx Tools/1. Xilinx Tools Introduction.mp41.33MB
  2. 10. Xilinx Tools/2. Download the Vivado Tool Suite for the BASYS 3.mp436.93MB
  3. 10. Xilinx Tools/3. ISim VHDL Simulation Tool.mp44.68MB
  4. 10. Xilinx Tools/4. Xilinx ISE FPGA Development Tool.mp49.23MB
  5. 10. Xilinx Tools/5. Programming The BASYS 2 FPGA Development Board.mp41.79MB
  6. 11. Lab 1 - Full Adder/1. Introduction.mp45.68MB
  7. 11. Lab 1 - Full Adder/2. BASYS 3 Full Adder Demonstration.mp487.88MB
  8. 11. Lab 1 - Full Adder/3. BASYS 2 Full Adder Demonstration.mp431.9MB
  9. 11. Lab 1 - Full Adder/4. BASYS 2 Full Adder Solution.mp438.67MB
  10. 12. Lab 2 - Shift Register/1. Introduction.mp45.67MB
  11. 12. Lab 2 - Shift Register/2. BASYS 3 Shift Register Demonstration.mp446.87MB
  12. 12. Lab 2 - Shift Register/3. BASYS 2 Shift Register Demonstration.mp437.7MB
  13. 13. Lab 3 - Universal Shift Register/1. Introduction.mp45.07MB
  14. 13. Lab 3 - Universal Shift Register/2. BASYS 3 Universal Shift Register Demonstration.mp470.63MB
  15. 13. Lab 3 - Universal Shift Register/3. BASYS 2 Universal Shift Register Demonstration.mp462.3MB
  16. 13. Lab 3 - Universal Shift Register/4. BASYS 2 Universal Shift Register Solution.mp469.65MB
  17. 14. Lab 4 - 7 Segment Display/1. Introduction.mp46.09MB
  18. 14. Lab 4 - 7 Segment Display/2. BASYS 3 - 7 Segment Display Demonstration.mp443.84MB
  19. 14. Lab 4 - 7 Segment Display/3. BASYS 2 - 7 Segment Display Demonstration.mp445.39MB
  20. 15. Lab 5 - Counter/1. Introduction.mp43.7MB
  21. 15. Lab 5 - Counter/2. BASYS 3 Counter Demonstration.mp424.67MB
  22. 15. Lab 5 - Counter/3. BASYS 2 Counter Demonstration.mp431.44MB
  23. 16. Lab 6 - Multiplier/1. Introduction.mp47.57MB
  24. 16. Lab 6 - Multiplier/2. BASYS 3 Multiplier Demonstration.mp4102.35MB
  25. 16. Lab 6 - Multiplier/3. BASYS 2 Multiplier Demonstration.mp461.87MB
  26. 17. Lab 7 - RC Servo/1. Introduction.mp421.31MB
  27. 17. Lab 7 - RC Servo/2. BASYS 3 RC Servo Demonstration.mp481.64MB
  28. 17. Lab 7 - RC Servo/3. BASYS 2 RC Servo Demonstration.mp425.91MB
  29. 2. Introduction/1. Introduction to the Course.mp435.18MB
  30. 2. Introduction/2. Introduction to VHDL.mp455.31MB
  31. 3. VHDL Data Types/1. Data Types Introduction.mp426.99MB
  32. 3. VHDL Data Types/2. Signals Variables Constants.mp441.58MB
  33. 3. VHDL Data Types/3. Unsigned Signed Data Types.mp447.51MB
  34. 3. VHDL Data Types/4. Standard Logic Vector Standard Logic.mp441.26MB
  35. 3. VHDL Data Types/5. Integer Boolean Data Types.mp434.61MB
  36. 3. VHDL Data Types/6. Initializing Values in VHDL.mp421.3MB
  37. 3. VHDL Data Types/7. Data Type Examples in VHDL Designs Part 1.mp414.9MB
  38. 3. VHDL Data Types/8. Data Type Examples in VHDL Designs Part 2.mp47.86MB
  39. 4. VHDL Syntax/2. If Statement Case Statement.mp476.21MB
  40. 4. VHDL Syntax/3. For Loop While Loop.mp470.39MB
  41. 4. VHDL Syntax/4. VHDL For Loop Example.mp48.07MB
  42. 4. VHDL Syntax/5. When Else Statement With Select When Statement.mp439.84MB
  43. 4. VHDL Syntax/6. VHDL Processes and Concurrent Statement.mp455.72MB
  44. 4. VHDL Syntax/7. VHDL Syntax Design Example.mp49.58MB
  45. 5. VHDL Coding Structure/1. Organizing Your VHDL Designs.mp411.4MB
  46. 5. VHDL Coding Structure/2. VHDL Design Structure.mp460.82MB
  47. 5. VHDL Coding Structure/3. VHDL Design Architecture Styles.mp497.46MB
  48. 5. VHDL Coding Structure/4. Data Flow Architecture Example - Full Adder.mp49.71MB
  49. 5. VHDL Coding Structure/5. Behavioral Architecture Example - Full Adder.mp47.19MB
  50. 6. Test Bench/1. Test Benches Introduction.mp446.33MB
  51. 6. Test Bench/2. Test Bench Structure Walkthrough.mp48.18MB
  52. 6. Test Bench/3. Walkthrough of a Completed Test Bench.mp410.58MB
  53. 7. Implementing State Machines in VHDL/1. State Machine Introduction.mp431.36MB
  54. 8. FPGA Development Boards/2. BASYS 3 Board Overview.mp484.42MB
  55. 8. FPGA Development Boards/5. BASYS 2 Board.mp43.91MB
  56. 8. FPGA Development Boards/8. BASYS 2 Board Overview.mp437.81MB
  57. 9. Altera Tools/1. Altera Tools Introduction.mp42.47MB
  58. 9. Altera Tools/2. ModelSim VHDL Simulation Tool.mp46.24MB
  59. 9. Altera Tools/3. Quartus II FPGA Development Tool.mp44.3MB
友情提示
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